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ISD3800 publica tion release date: sep 22, 2010 - 1 - revision 0.60 ISD3800 digital chipcorder with digital audio interface
ISD3800 publica tion release date: sep 22, 2010 - 2 - revision 0.60 table of contents 1 general description ............................... ................................................... ............................ 3 2 features .......................................... ................................................... ......................................... 3 3 block diagram ..................................... ................................................... ................................... 5 4 pinout configuration .............................. ................................................... ........................... 6 4.1 48l-lqfp .......................................... ................................................... ................................................... 6 5 pin description ................................... ................................................... .................................... 7 6 electrical characteristics ........................ ................................................... ................... 11 6.1 o perating c onditions .................................................. ................................................... ................... 11 6.2 dc p arameters .................................................. ................................................... .............................. 12 6.3 ac p arameters .................................................. ................................................... .............................. 13 6.3.1 inputs ............................................ ................................................... .............................................. 13 6.3.2 outputs ........................................... ................................................... ............................................. 14 6.3.3 spi timing ........................................ ................................................... .......................................... 17 6.3.4 i 2 s timing .......................................... ................................................... ......................................... 18 7 application diagram ............................... ................................................... ............................ 20 8 package specification ............................. ................................................... ......................... 22 8.1 48 l ead lqfp(7 x 7 x 1.4 mm footprint 2.0 mm ) ................................................. ................................... 22 9 ordering information .............................. ................................................... ......................... 23 10 revision history................................... ................................................... ............................ 24
ISD3800 publica tion release date: sep 22, 2010 - 3 - revision 0.60 1 general description the ISD3800 is a digital chipcorder ? featuring digital compression, comprehensive memor y management, and integrated analog/digital audio sig nal paths. the ISD3800 utilizes serial flash memory to provide non-volatile audio playback for a two-chip solution. the ISD3800 provides an i 2 s digital audio interface, faster digital programming , higher sampling frequency, and a signal path with snr 80db. the ISD3800 can take digital audio data via i 2 s or spi interface. when i 2 s input is selected, it will replace the analog audio inputs and will support sa mple rates of 32, 44.1 or 48 khz depending upon clock configuration. when spi interface is chosen, the sample rate of the audio data sent must be one of the ISD3800 supported sample rates. the ISD3800 has inbuilt analog audio inputs, analog audio line driver, and speaker driver output. the analog audio input, aux-in, has a fixed gain co nfigured by spi command. aux-in can directly feed-through to the analog outputs; it can also mix with the dac output and then feed-through to the analog outputs. analog outputs are available in two forms: (1) aux- out is an analog single-ended voltage output; (2) class-ab btl (bridge-tied-load) is an analog differ ential voltage output. class-ab btl delivers 1-wat t output power at v ccspk = 5v. class-d pwm direct-drive is also available, which d elivers 1-watt output power at v ccspk = 5v. 2 features external memory: o the ISD3800 supports the following flash: manufacturer winbond numonyx mxic family 25x 25q 25p 25px 25pe 25l / 25v jedec id ef 30 1x ef 40 1x 20 20 1x 20 71 1x 20 80 1x c2 20 1x o the addressing ability of ISD3800 is up to 128mbit , which is 64-minute playback time based on 8khz/4bit adpcm. o inbuilt 3v voltage regulator to provide power sour ce to the external flash memory fast digital programming o programming rate can go up to 1mbits/second mainly limited by the flash memory write rate. memory management o store pre-recorded audio (voice prompts) using hig h quality digital compression o use a simple index-based command for playback o execute pre-programmed macro scripts (voice macros ) designed to control the configuration of the device and play back voice prompts sequences . sample rate o seven sampling frequencies are available for a giv en master sample rate. for example, the sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16 an d 32khz are available when the device is clocked at a 32khz master sample rate. o for i 2 s operation, 32, 44.1 and 48khz master sample rates are available with playback sampling frequencies scaling accordingly. compression algorithms o for pre-recorded voice prompts -law: 6, 7 or 8 bits per sample
ISD3800 publica tion release date: sep 22, 2010 - 4 - revision 0.60 differential -law: 6, 7 or 8 bits per sample pcm: 8, 10 or 12 bits per sample enhanced adpcm: 2, 3, 4 or 5 bits per sample variable-bit-rate optimized compression. this all ows best possible compression given a metric of snr and background noise levels. oscillator o internal oscillator with internal reference: 2.048 mhz o internal oscillator with external resistor: 2.048 mhz with rosc = 80kohm o external crystal or clock input crystals support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288 and 11.2896mhz o i 2 s bit clock input inputs o aux-in: analog input with 2-bit gain control confi gured by spi command outputs o pwm: class-d speaker driver to directly drive an 8 speaker or buzzer deliver 1-watt output power at v ccspk = 5v o aux-out: an analog single-ended voltage output o class -ab btl: an analog differential voltage output deliver 1-watt output power at v ccspk = 5v class-ab btl can directly drive an 8 speaker or buzzer class-ab btl can drive an 8 speaker or buzzer via an external amplifier i/os o spi interface: miso, mosi, sclk, ssb for commands and digital audio data o i 2 s interface: i 2 s_clk, i 2 s_ws, i 2 s_sdi, i 2 s_sdo for digital audio data o 8 gpio pins: 4 gpio pins share with i 2 s 4 gpio pins share with spi interface gpio pins can trigger voice macro for a pushbutton application 8-bit volume control set by spi command for flexib le mixing operating voltage: 2.7 ~ 5.5v standby current: 1ua typical package: o green 48l-lqfp temperature options: o industrial: -40 c to 85 c
ISD3800 publica tion release date: sep 22, 2010 - 5 - revision 0.60 3 block diagram auxin digitalsignalpath: digitalfilters resampling volumecontrol dac + auxout pwm control decompression flashmemory controller i2s interface spi interface memorymanagement andcommand interpreter sck sdi ws auxout sum2 sdo aux_mux gpio4/ gpio5/ gpio6/ gpio7/ a v = 0 , 3 , 6 , 9 d b auxin spk+_mux spk_mux fclk fcsb fdi fdo sclk rdy/bsyb intb mosi miso ssb gpio1/ gpio0/ gpio3/ gpio2/ spk+ spk figure 3-1 ISD3800 block diagram
ISD3800 publica tion release date: sep 22, 2010 - 6 - revision 0.60 4 pinout configuration 4.1 48l-lqfp figure 4-1 ISD3800 48-lead lqfp pin configuration.
ISD3800 publica tion release date: sep 22, 2010 - 7 - revision 0.60 5 pin description pin number 48l- lqfp pin name i/o function 1 nc this pin should be left unconnected. 2 nc this pin should be left unconnected. 3 nc this pin should be left unconnected. 4 gpio7 / i 2 s_sdi i/o a gpio pin. by default this pin is a pull-high input. can be configured as serial data input of the i 2 s interface. 5 gpio6 / i 2 s_sck i/o a gpio pin. by default this pin is a pull-high input. can be configured as clock input in slave mode or c lock output in master mode. this pin can be configured as an exter nal clock buffer if i 2 s is not used. 6 gpio5 / i 2 s_ws i/o a gpio pin. by default this pin is a pull-high input. can be configured as word select (ws) input in slav e mode or ws output in master mode. 7 gpio4 / i 2 s_sdo i/o a gpio pin. by default this pin is a pull-high input. can be configured as serial data output of the i 2 s interface. 8 nc this pin should be left unconnected. 9 nc this pin should be left unconnected. 10 v ssd i digital ground. 11 v ccd i digital power supply. 12 v reg o a 1.8v regulator to supply the internal logic. a minimum 1uf capacitor with low esr<0.5ohm should be connected t o this pin for supply decoupling and stability. 13 miso / gpio1 o master-in-slave-out. serial output from the isd38 00 to the host. this pin is in tri-state when ssb=1. can be configured as gpio1. 14 sclk i serial clock input to the ISD3800 from th e host. 15 ssb i slave select input to the ISD3800 from the host. when ssb is low device is selected and responds to commands on the spi interface. 16 mosi / gpio0 i master-out-slave-in. serial input to the ISD3800 from the host. can be configured as gpio0.
ISD3800 publica tion release date: sep 22, 2010 - 8 - revision 0.60 pin number 48l- lqfp pin name i/o function 17 v ccspk i in pwm mode: digital power for the pwm driver. deliver 1-watt output power at v ccspk = 5v. or, in class-ab mode: analog power for the class-ab out put. class-ab btl delivers 1-watt output power at v ccspk = 5v. 18 spk+ o pwm driver positive output. this spk+ ou tput, together with spk- pin, provide a differential output to drive 8 speaker or buzzer. during power down this pin is in tri-state. or, can be configured as class-ab btl which, togeth er with spk- pin, provides a differential voltage output. or, can be configured as a class-ab single-ended ou tput. 19 v ssspk i in pwm mode: digital ground for the pwm driver. or, in class-ab mode: analog ground for the class-ab ou tput. 20 spk- o pwm driver negative output. this spk- ou tput, together with spk+ pin, provides a differential output to drive 8 speaker or buzzer. during power down this pin is tri-state. or, can be configured as class-ab btl which, togeth er with spk+ pin, provides a differential voltage output. or, can be configured as a class-ab single-ended ou tput. 21 v ccspk i in pwm mode: digital power for the pwm driver. deliver 1-watt output power at v ccspk = 5v. or, in class-ab mode: analog power for the class-ab out put. class-ab btl delivers 1-watt output power at v ccspk = 5v. 22 nc this pin should be left unconnected. 23 nc this pin should be left unconnected. 24 nc this pin should be left unconnected. 25 intb / gpio3 o active low interrupt request pin. this pin is an open-drain output. can be configured as gpio3. 26 rdy/bsyb / gpio2 o an output pin to report the status of data transf er on the spi interface. high indicates that ISD3800 is ready t o accept new spi commands or data. can be configured as gpio2. 27 reset i applying power to this pin will reset th e chip. (a high pulse of 50ms or more will reset the chip.)
ISD3800 publica tion release date: sep 22, 2010 - 9 - revision 0.60 pin number 48l- lqfp pin name i/o function 28 fdo o serial data output of the external serial flash interface. connects to data input (di) of external serial flash. 29 fclk o serial data clk of the external serial fl ash interface. 30 fdi i serial data input to external serial flash interface. connects to data output (do) of external flash memory. 31 fcsb o chip select bar of the external serial fl ash interface. 32 v ccf o digital power supply for the external flash memo ry. a minimum 1uf capacitor with low esr<0.5ohm should be connected t o this pin for supply decoupling and stability. refer to the appl ication diagram. 33 v ccf o digital power supply for the external flash memo ry. a minimum 1uf capacitor with low esr<0.5ohm should be connected t o this pin for supply decoupling and stability. refer to the appl ication diagram. 34 v ccfs i digital power supply for the inbuilt voltage reg ulator for the external flash memory. a 0.1uf capacitor should be connecte d to this pin for supply decoupling and stability. refer to the appl ication diagram. 35 xtalout o crystal interface output pin. 36 xtalin i the clk_cfg register determines one of the following three configurations: (1) a crystal or resonator connecte d between the xtalout and xtalin pins. (2) a resistor connected t o gnd as a reference current to the internal oscillator and le ft the xtalout unconnected. (3) an external clock input to the dev ice and left the xtalout unconnected. 37 nc this pin should be left unconnected. 38 nc this pin should be left unconnected. 39 nc this pin should be left unconnected. 40 nc this pin should be left unconnected. 41 nc this pin should be left unconnected. 42 aux-out o aux out. this pin is an analog voltag e output. if auxout is not used, this pin should be left unco nnected. 43 v cca i analog power supply pin. 44 v ssa i analog ground pin. 45 v mid o middle voltage reference for the swing of analog /digital audio outputs. a 4.7uf capacitor should be connected to this pin for supply decoupling and stability. 46 nc this pin should be left unconnected.
ISD3800 publica tion release date: sep 22, 2010 - 10 - revision 0.60 pin number 48l- lqfp pin name i/o function 47 aux-in i auxiliary input with the gain set by sp i command if aux-in is not used, this pin should be left unco nnected. 48 nc this pin should be left unconnected.
ISD3800 publica tion release date: sep 22, 2010 - 11 - revision 0.60 6 electrical characteristics 6.1 o perating c onditions operating conditions (industrial packaged parts) conditions values operating temperature range (case temperature) -40 c to +85c digital supply voltage (v ccd ) [1] +2.7v to +5.5v digital ground voltage (v ssd ) [2] 0v analog supply voltage (v cca ) [3] +2.7v to +5.5v analog ground voltage (v ssa ) [2] 0v speaker supply voltage (v ccspk ) [3] +2.7v to +5.5v speaker ground voltage (v ssspk ) [2] 0v flash source supply voltage (v ccfs ) [4] C to regulate v ccf +2.7v to +5.5v flash source supply voltage (v ccfs ) [4] C tied to v ccf +2.25v to +3.6v flash supply voltage - (v ccf ) [4] C regulated from v ccfs +2.4v to +3.0v flash supply voltage - (v ccf ) [4] C tied to v ccfs +2.25v to +3.6v notes: [1] v ccd 2.7 ~ 5.5v; no restrictions with respect to v cca and v ccspk . [2] v ssd = v ssa = v ssspk [3] in class-ab mode: v ccspk must equal v cca . otherwise: v ccspk v cca . [4] if v ccfs is guaranteed to be below 3.6v (or upper flash sup ply limit), then v ccf should be tied to v ccfs . figure 6-1 v ccf vs. v ccfs C v ccf is regulated internally from v ccfs [4]
ISD3800 publica tion release date: sep 22, 2010 - 12 - revision 0.60 6.2 dc p arameters parameter symbol min typ [1] max unit s conditions digital supply voltage v ccd 2.7 5.5 v analog supply voltage v cca 2.7 5.5 v speaker supply voltage v ccspk 2.7 5.5 v flash source supply voltage v ccfs 2.7 5.5 v to regulate v ccf 2.25 3.6 tied to v ccf flash supply voltage (refer to figure 6-1) v ccf v ccfs -0.3 v regulated from v ccfs v ccfs = 2.7 ~ 3.3v 3.0 regulated from v ccfs v ccfs = 3.3 ~ 5.5v 2.25 3.6 tied to v ccfs input low voltage v il v ssd -0.3 0.3xv ccd v input high voltage v ih 0.7xv ccd v ccd v output low voltage v ol v ssd -0.3 0.3xv ccd v i ol = 1ma output high voltage v oh 0.7xv ccd v ccd v i oh = -1ma intb output low voltage v oh1 0.4 v playback current i dd_playback 30 ma standby current i sb 1 10 a input leakage current i il 1 a force v ccd notes: [1] conditions v ccd =v cca =v ccspk =v ccfs =3v, t a =25c unless otherwise stated
ISD3800 publica tion release date: sep 22, 2010 - 13 - revision 0.60 6.3 ac p arameters 6.3.1 inputs aux-in: conditions: v ccd = 3.3v, v cca = v ccspk = 5v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units auxiliary analog inputs (auxin) full scale input signal 1 gain = 0db 1.0 0 vrms dbv aux programmable gain 0 9 db aux programmable gain step size guaranteed monotonic 3 db input resistance aux direct-to-out path, only input gain = +9.0db input gain = +6.0db input gain = +3.0db input gain = 0db 21 27 33 40 k k k k aux-in gain accuracy a aux(ga) -0.5db +0.5db db conditions: v ccd = 3.3v, v cca = v ccspk = 3.3v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units auxiliary analog inputs (auxin) full scale input signal 1 gain = 0db 1.0 0 vrms dbv aux programmable gain 0 9 db aux programmable gain step size guaranteed monotonic 3 db input resistance raux_in aux direct-to-out path, only input gain = +9.0db input gain = +6.0db input gain = +3.0db input gain = 0db 21 27 33 40 k k k k aux-in gain accuracy a aux(ga) -0.5db +0.5db db
ISD3800 publica tion release date: sep 22, 2010 - 14 - revision 0.60 6.3.2 outputs aux-out conditions: v ccd = 3.3v, v cca = v ccspk = 5v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units digital to analog converter (dac) driving auxout w ith 5k / 100pf load full-scale output gain paths all at 0db gain v cca / 3.3 v rms signal-to-noise ratio snr a-weighted 85 db total harmonic distortion 2 thd+n r l = 5k ; full-scale signal a-weighted -80 db conditions: v ccd = 3.3v, v cca = v ccspk = 3.3v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units digital to analog converter (dac) driving auxout w ith 5k / 100pf load full-scale output gain paths all at 0db gain v cca / 3.3 v rms signal-to-noise ratio snr a-weighted 80 db total harmonic distortion 2 thd+n r l = 5k ; full-scale signal a-weighted -77 db
ISD3800 publica tion release date: sep 22, 2010 - 15 - revision 0.60 pwm output conditions: v ccd = 3.3v, v cca = v ccspk = 5v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units speaker pwm output (spk_plus / spk_minus with 8 bridge-tied-load) signal-to-noise ratio 3 snr a-weighted + class d filter 65 db total harmonic distortion 2 thd p o = 1w, a-weighted + class d filter -40 db efficiency e pwm 8 bridge-tied-load pout > 0.2w 85 % conditions: v ccd = 3.3v, v cca = v ccspk = 3.3v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units speaker pwm output (spk_plus / spk_minus with 8 bridge-tied-load) signal-to-noise ratio 3 snr a-weighted + class d filter 65 db total harmonic distortion 2 thd a-weighted + class d filter -40 db efficiency e pwm 8 bridge-tied-load pout > 0.2w 80 % figure 6-2 pwm power vs. v ccspk
ISD3800 publica tion release date: sep 22, 2010 - 16 - revision 0.60 class-ab btl output conditions: v ccd = 3.3v, v cca = v ccspk = 5v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units speaker class-ab btl output (spk_plus / spk_minus w ith 8 bridge-tied-load) full scale output gain paths all at 0db gain v cca / 3.3 v rms signal-to-noise ratio snr a-weighted 90 db total harmonic distortion 2 thd p o = 1w, a-weighted -60 db efficiency e ab 8 bridge-tied-load pout > 0.7w 50 % conditions: v ccd = 3.3v, v cca = v ccspk = 3.3v , mclk = 16.384mhz, t a = +25c, 1khz signal parameter symbol comments/conditions min typ max units speaker class-ab btl output (spk_plus / spk_minus w ith 8 bridge-tied-load) full scale output gain paths all at 0db gain v cca / 3.3 v rms signal-to-noise ratio snr a-weighted 84 db total harmonic distortion 2 thd a-weighted -60 db efficiency e ab 8 bridge-tied-load pout > 0.4w 50 % figure 6-3 class-ab btl power vs. v ccspk notes 1. full scale is relative to the magnitude of vcca and can be calculated as fs = vcca/3.3. 2. distortion is measured in the standard way as th e combined quantity of distortion products plus noi se. the signal level for distortion measurements is at 3db below f ull scale, unless otherwise noted. 3. snr measured with a -100dbfs signal at input.
ISD3800 publica tion release date: sep 22, 2010 - 17 - revision 0.60 6.3.3 spi timing t rise t fall ssb sclk mosi miso t sck t sckh t sckl t ssbs t ssbh t mos t moh t mid t ssbhi t zmid rdy/bsyb t crbd t rbcd t mizd figure 6-4 spi timing symbol description min typ max unit t sck sclk cycle time 60 --- --- ns t sckh sclk high pulse width 25 --- --- ns t sckl sclk low pulse width 25 --- --- ns t rise rise time for all digital signals --- --- 10 ns t fall fall time for all digital signals --- --- 10 ns t ssbs ssb falling edge to 1 st sclk falling edge setup time 30 --- --- ns t ssbh last sclk rising edge to ssb rising edge hold time 30ns --- 50us --- t ssbhi ssb high time between ssb lows 20 --- --- ns t mos mosi to sclk rising edge setup time 15 --- --- ns t moh sclk rising edge to mosi hold time 15 --- --- ns t zmid delay time from ssb falling edge to miso active - - -- 12 ns t mizd delay time from ssb rising edge to miso tri-state -- -- 12 ns
ISD3800 publica tion release date: sep 22, 2010 - 18 - revision 0.60 symbol description min typ max unit t mid delay time from sclk falling edge to miso --- --- 12 ns t crbd delay time from sclk rising edge to rdy/bsyb falling edge -- -- 12 ns t rbcd delay time from rdy/bsyb rising edge to sclk falling edge 0 -- -- ns 6.3.4 i 2 s timing t wsh t wss msb t sdis t sdod t sckh t sckl t wsh t wss msb msb msb lsb lsb t sdih t sck t rise t fall is_sck is_ws is_sdi is_sdo figure 6-5 i 2 s timing symbol description min typ max unit t sck is_sck cycle time 60 --- --- ns t sckh is_sck high pulse width 25 --- --- ns t sckl is_sck low pulse width 25 --- --- ns t rise rise time for all digital signals --- --- 10 ns t fall fall time for all digital signals --- --- 10 ns
ISD3800 publica tion release date: sep 22, 2010 - 19 - revision 0.60 symbol description min typ max unit t wss ws to is_sck rising edge setup time 20 --- --- ns t wsh is_sck rising edge to is_ws hold time 20 --- --- n s t sdis is_sdi to is_sck rising edge setup time 15 --- --- ns t sdih is_sck rising edge to is_sdi hold time 15 --- --- ns t sdod delay time from is_sclk falling edge to is_sdo -- - --- 12 ns
ISD3800 publica tion release date: sep 22, 2010 - 20 - revision 0.60 7 application diagram i 2 s_sdi/gpio7 i 2 s_sck/gpio6 i 2 s_ws/gpio5 i 2 s_sdo/gpio4 4 5 6 7 miso/gpio1 sclk ssb mosi/gpio0 intb/gpio3 rdy/bsyb/gpio2 reset 13 14 15 16 25 26 27 auxin v ssd v ccd v ccd highpulseof50ms :digitalground; :analogground; 47 v ccd 10k dataflowcontrol spitypeiii 100 4.7k 0.1uf 200 pf auxout 42 43 v ssa v cca 0.1 uf v cca 44 csb do wpb gnd vcc holdb clk dio flash fdi fcsb fclk fdo 29 28 11 10 0.1 uf 30 31 v ccfs v ccf 34 32 10k 33 v ccf 5.6k 5.6k 220pf 0.1uf :groundforspk; 0.1 uf v ccspk 17 21 19 v ssspk v ccspk v ccspk spk+ spk 18 20 v mid 45 4.7 uf v reg 12 1uf 1uf 0.1 uf 47 uf v ccd v cca v ccspk 0 0 1uh 1uh xtalout xtalin 36 35 27pf 27pf 270 ISD3800 figure 7-1 ISD3800 application diagram C v ccf is regulated internally from v ccfs
ISD3800 publica tion release date: sep 22, 2010 - 21 - revision 0.60 figure 7-2 ISD3800 application diagram C v ccf is tied to v ccfs the above application examples are for references o nly. it makes no representation or warranty that s uch applications shall be suitable for the use spec ified. each design has to be optimized in its own system for the best performance on voice qu ality, current consumption, functionalities and etc .
ISD3800 publica tion release date: sep 22, 2010 - 22 - revision 0.60 8 package specification 8.1 48 l ead lqfp(7 x 7 x 1.4 mm footprint 2.0 mm )
ISD3800 publica tion release date: sep 22, 2010 - 23 - revision 0.60 9 ordering information i3800 fyi lead-free package type f: 48l-lqfp y: green (rohs compliant) i: industrial -40 c to 85 c
ISD3800 publica tion release date: sep 22, 2010 - 24 - revision 0.60 10 revision history version date description 0.23 aug 3, 2009 initially released as the prelimin ary datasheet. 0.26 aug 17, 2009 update application diagram. 0.27 sep 28, 2009 update the list of supported flas h memory. 0.29 nov 18, 2009 update: block diagram. electrical characteristics. 0.35 feb 8, 2010 update block diagram. 0.40 july 1, 2010 update crystal configuration. 0.50 aug 12, 2010 update pwm spec. 0.60 sep 22, 2010 update ordering information.
ISD3800 publica tion release date: sep 22, 2010 - 25 - revision 0.60 nuvoton products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy c ontrol instruments, airplane or spaceship instrumen ts, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications int ended to support or sustain life. furthermore, nuvoton products are not intended for applications wherein failure of nuvot on products could result or lead to a situation wherein personal inju ry, death or severe property or environmental damag e could occur. nuvoton customers using or selling these products f or use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from su ch improper use or sales. the contents of this document are provided only as a guide for the applications of nuvoton products. n uvoton makes no representation or warranties with respect to the ac curacy or completeness of the contents of this publ ication and reserves the right to discontinue or make changes t o specifications and product descriptions at any ti me without notice. no license, whether express or implied, to any inte llectual property or other right of nuvoton or othe rs is granted by this publication. except as set forth in nuvoton's stan dard terms and conditions of sale, nuvoton assumes no liability whatsoever and disclaims any express or implied war ranty of merchantability, fitness for a particular purpose or infringement of any intellectual property. the contents of this document are provided as is, and nuvoton assumes no liability whatsoever and di sclaims any express or implied warranty of merchantability, fit ness for a particular purpose or infringement of an y intellectual property. in no event, shall nuvoton be liable for any damages whatsoever (including, without limitati on, damages for loss of profits, business interruption, loss of inf ormation) arising out of the use of or inability to use the contents of this documents, even if nuvoton has been advised of the possibility of such damages. application examples and alternative uses of any in tegrated circuit contained in this publication are for illustration only and nuvoton makes no representation or warranty tha t such applications shall be suitable for the use s pecified. the 100-year retention and 100k record cycle projec tions are based upon accelerated reliability tests, as published in the nuvoton reliability report, and are neither war ranted nor guaranteed by nuvoton. this datasheet and any future addendum to this data sheet is(are) the complete and controlling isd ? chipcorder ? product specifications. in the event any inconsist encies exist between the information in this and ot her product documentation, or in the event that other product d ocumentation contains information in addition to th e information in this, the information contained herein supersedes a nd governs such other information in its entirety. this datasheet is subject to change without notice. copyright ? 2005, nuvoton technology corporation. all rights reserved. chipcorder ? and isd ? are trademarks of nuvoton technology corporation. all other trademark s are properties of their respective owners. headquarters nuvoton technology corporation america nuvoton technology (shanghai) ltd. no. 4, creation rd. iii 2727 north first st reet, san jose, 27f, 299 yan an w. rd. shan ghai, science-based industrial park, ca 95134, u.s.a . 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1-408-5441797 fax: 86-21-62356998 fax: 886-3-5665577 http://www.nuvoton-usa.c om/ http://www.nuvoton.com.tw/ taipei office nuvoton technology corporation japan nuvoton technology (h.k.) ltd. 9f, no. 480, pueiguang rd. 7f daini-ueno bld g. 3-7-18 unit 9-15, 22f, millennium city, neihu district shinyokohama kohokuku, no. 378 kwun tong rd., taipei, 114 taiwan yokohama, 222-0033 kowloon, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-2-87153579 fax: 81-45-4781800 fax: 852-27552064 please note that all data and specifications are su bject to change without notice. all the trademarks of products and companies mentio ned in this datasheet belong to their respective ow ners.

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